The system physically contains 4.5 MB of RAM, however, it’s connected using a 9-bit data bus where the 9th bit is reserved for the GPU (more details in the ‘Graphics’ section). Memory designĪpart from the UMA, the structure of RAM is a little bit complicated, so I’ll try to keep it simple. No DMA controller?ĭue to the unified memory architecture, the CPU no longer has direct access to RAM, so the GPU will be providing DMA functionality as well. The reason for choosing this design comes from the fact that it saves a considerable amount of production costs while, on the other side, it increments access contention if not managed properly. The component arbitrating its access is, in this case, the GPU. The way RAM is assembled follows the unified-memory architecture or ‘UMA’ where all available RAM is centralised in one place only and any component that requires RAM will access this shared location. Though it contains a dedicated register file and will speed up operations with 64-bit and 32-bit floating-point numbers. The VR4300 identifies it as a co-processor (CP1), however, the unit is fitted next to the ALU and it’s only accessed through the CPU’s internal ALU pipeline, meaning there’s no co-processing per se. 24 KB L1 cache: Divided into 16 KB for instructions and 8 KB for data.Īn internal Floating-point Unit (FPU) is also included in this package.
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